Keysight Technologies has launched PathWave Advanced Design System (ADS) 2023 for high-speed digital (HSD) design with new Memory Designer capabilities for modeling and simulation of next-generation interface standards such as Double Data Rate 5 (DDR5).
As data center throughput climbs, performance expectations of servers and high-performance computing drive the need for new high-density, ultra-fast memory or DDR5 Dynamic Random Access Memory (DRAM).
Operating at twice the data rate of DDR4 memory results in shrinking design margins and makes it difficult for hardware designers to optimize printed circuit boards (PCB) to minimize the effects of reflection, crosstalk and jitter.
In addition, lower voltages, higher currents and new requirements for equalization within the DRAM receiver create signal integrity challenges that are difficult and costly to troubleshoot.
Keysight’s PathWave ADS 2023 for HSD ensures rapid simulation setup and advanced measurements while providing designers critical insights to overcome signal integrity challenges.
Its new Memory Designer constructs parameterized memory buses using the new pre-layout builder, allowing designers to explore system trade-offs that reduce design time and de-risk product development for DDR5, Low-Power Double Data Rate (LPDDR5 / 5x), and Graphics Double Data Rate (GDDR6 / 7) memory systems.
“The biggest takeaway from our first DDR5 design is just how many aspects there are to consider with simulation,” said Lorenzo Forni, PCB design and SI/PI leader at SECO, an Italian industrial group that designs and produces embedded systems and IoT solutions.
“You must combine the stack-up analysis, routing geometry and the AMI